The present invention relates generally to the semiconductor devices and the fabrication thereof and, more particularly, to a semiconductor device fabricated with the use of a high-K liner.
Fabrication of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFET) and complementary metal oxide semiconductor (CMOS) integrated circuits, involves numerous processing steps. Each step may potentially have an adverse effect on one or more device components.
In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in a layer of semiconductor material. Disposed between the source and drain is a body region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on a insulating layer that is, in turn, disposed on a silicon substrate).
A pervasive trend in modern integrated circuit manufacture is to produce transistors, and the structural features thereof, that are as small as possible. Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, slight imperfections in the formation of the component parts of a transistor can lead to poor transistor performance and failure of the overall circuit. As an example, during the fabrication process, certain unwanted portions of various device layers are removed using wet chemical etching and/or dry etching (e.g., reactive ion etching (RIE)) techniques. During the etching process desired portions of other layers may become damaged. Such damage can lead to a reduction in the operational performance of the device being fabricated.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that are formed using techniques intended to minimize imperfections in the resulting device.
According to one aspect of the invention, the invention is directed to a semiconductor device. The semiconductor device includes a layer of semiconductor material having an active region defined by at least one isolation region. A gate is disposed on the layer of semiconductor material, the gate including a gate dielectric and a gate electrode, the gate electrode spaced from the layer of semiconductor material by the gate dielectric and the gate defining sidewalls. A sidewall spacer is disposed adjacent each sidewall of the gate and each sidewall spacer extending laterally from the gate over the layer of semiconductor material. The semiconductor device also includes a liner composed of a high-K material, the liner having portions separating the sidewall spacers and the gate and the liner having portions separating the sidewall spacers and the layer of semiconductor material, the liner functioning as an etch stop during formation of the sidewall spacers and the liner being removable by an etch process that has substantially no reaction with the at least one isolation regions.
According to another aspect of the invention, the invention is directed to a method of fabricating a semiconductor device. The method includes the steps of providing a layer of semiconductor material; forming at least one isolation region in the layer of semiconductor material; forming a gate including a gate dielectric and a gate electrode over the layer of semiconductor material, the gate electrode spaced from the layer of semiconductor material by the gate dielectric and the gate defining sidewalls; forming a liner composed of a high-K material adjacent the sidewalls of the gate and extending laterally from the gate over the layer of semiconductor material; depositing a layer of sidewall spacer material over the liner; anisotropically etching the layer of sidewall spacer material to form a sidewall spacer adjacent each sidewall of the gate and using the liner as an etch stop for controlling etching of the layer of sidewall spacer material; implanting dopant species to form deep doped regions of a source and a drain in the layer of semiconductor material; and removing at least a portion of the liner to open the source and the drain for formation of a source contact and a drain contact, the portion of the liner removed using an etch process that has substantially no reaction with the isolation regions.